Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 559 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Figures 16.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 16.25 (when
TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM
waveforms with duty cycles of 0% and 100% in PWM mode.
GRA
TRDCNT value
0% duty
0% duty
Time
Time
Time
GRB rewritten
TRDCNT value
GRB rewritten
GRB
rewritten
GRB rewritten
TRDCNT value
GRB rewritten
GRB rewritten
GRB rewritten
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
GRB rewritten
100% duty
100% duty
GRB
H'0000
FTIOB
GRA
GRB
H'0000
FTIOB
GRA
GRB
H'0000
FTIOB
Figure 16.24 Example of PWM Mode Operation (3)