Datasheet

Section 16 Timer RD
Page 550 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
GRB
GRA
H'0000
FTIOB
Toggle output
Toggle output
Time
TRDCNT value
FTIOA
Figure 16.14 Example of Toggle Output Operation
(2) Output Compare Timing
The compare match signal is generated in the last state in which TRDCNT and GR match (when
TRDCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TRDIOR is output at the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD). When TRDCNT matches GR, the compare match signal is
generated only after the next TRDCNT input clock pulse is input.
Figure 16.15 shows an example of the output compare timing.
TRDCNT input
φ
Compare match
signal
TRDCNT
GR
N
N
N+1
FTIOA to FTIOD
Figure 16.15 Output Compare Timing