Datasheet

Section 16 Timer RD
Page 548 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• External clock operation
An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TRDCR, and
a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the
rising edge, falling edge, or both edges can be selected.
Figure 16.11 illustrates the detection timing of the rising and falling edges.
TRDCNT
External clock
input pin
TRDCNT input
N-1 N N+1
φ
Figure 16.11 Count Timing in External Clock Operation (Both Edges Detected)
16.3.2 Waveform Output by Compare Match
Timer RD can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or
FTIOD output pin using compare match A, B, C, or D.
Figure 16.12 shows an example of the setting procedure for waveform output by compare match.
[1] Select 0 output, 1 output, or toggle
output as a compare much output, by
means of TRDIOR. The initial values set
in TRDOCR are output unit the first
compare match occurs.
[2] Set the timing for compare match
generation in GRA/GRB/GRC/GRD.
[3] Enable or disable the timer output by
TRDOER1.
[4] Set the STR bit in TRDSTR to 1 to start
the TRDCNT count operation.
[1]
Output selection
Select waveform output mode
[2]
Set output timing
[3]
Enable waveform output
[4]
Start count operation
<Waveform output>
Figure 16.12 Example of Setting Procedure for Waveform Output by Compare Match