Datasheet

Section 16 Timer RD
Page 546 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(1) Free-Running Count Operation and Periodic Count Operation
Immediately after a reset, the TRDCNT counters for channels 0 and 1 are all designated as free-
running counters. When the relevant bit in TRDSTR is set to 1, the corresponding TRDCNT
counter starts an increment operation as a free-running counter. When TRDCNT overflows, the
OVF flag in TRDSR is set to 1. If the value of the OVIE bit in the corresponding TRDIER is 1 at
this point, timer RD requests an interrupt. After overflow, TRDCNT starts an increment operation
again from H'0000.
Figure 16.8 illustrates free-running counter operation.
H'FFFF
TRDCNT value
Time
H'0000
STR0,
STR1
OVF
Figure 16.8 Free-Running Counter Operation
When compare match is selected as the TRDCNT clearing source, the TRDCNT counter for the
relevant channel performs periodic count operation. The GR registers for setting the period are
designated as output compare registers, and counter clearing by compare match is selected by
means of bits CCLR1 and CCLR0 in TRDCR. After the settings have been made, TRDCNT starts
an increment operation as a periodic counter when the corresponding bit in TRDSTR is set to 1.
When the count value matches the value in GR, the IMFA, IMFB, IMFC, or IMFD flag in TRDSR
is set to 1 and TRDCNT is cleared to H'0000. If the value of the corresponding IMIEA, IMIEB,
IMIEC, or IMIED bit in TRDIER is 1 at this point, timer RD requests an interrupt. After a
compare match, TRDCNT starts an increment operation again from H'0000.