Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 531 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
0 IMFA Input capture/
compare
match flag A
[Setting conditions]
• When TRDCNT = GRA and GRA is functioning
as output compare register
• When TRDCNT = GRA in PWM mode, PWM3
mode, reset synchronous PWM mode, or
complementary PWM mode (in reset
synchronous PWM mode, however, while
TRDCNT_0 = GRA_1 and TRDCNT_0 = GRA_0)
• When TRDCNT value is transferred to GRA by
input capture signal and GRA is functioning as
input capture register
[Clearing conditions]
• When the DTC is activated by an IMFA interrupt
and the DISEL bit in MRB of the DTC is 0
• When 0 is written to IMFA after reading IMFA = 1
R/W
Note: * Bit 5 is not the UDF flag in TRDSR_0. It is a reserved bit. It is always read as 1.
TRDSR is each interrupt request flag of the timer RD. If an interrupt is enabled by a
corresponding bit in TRDIER, TRDSR requests an interrupt for the CPU. Timer RD has two
TRDSR registers, one for each channel.