Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 529 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.2.13 Timer RD Status Register (TRDSR)
Address:
Bit:
Value after reset:
b7
⎯
1
b6
⎯
1
b5
UDF
0
b4
OVF
0
b3
IMFD
0
b2
IMFC
0
b1
IMFB
0
b0
IMFA
0
H'FFFFC7, H'FFFFCE
Bit Symbol Bit Name Description R/W
7, 6 ⎯ Reserved These bits are read as 1. The write value should be
1.
⎯
5 UDF* Underflow flag
0: TRDCNT_1 has not underflowed.
1: TRDCNT_1 has underflowed.
[Setting condition]
• When TRDCNT underflows
[Clearing condition]
• When 0 is written to UDF after reading UDF = 1
R/W
4 OVF Overflow flag
0: TRDCNT has not overflowed.
1: TRDCNT has overflowed.
[Setting condition]
• When TRDCNT value is underflowed
[Clearing condition]
When 0 is written to OVF after reading OVF = 1
R/W
3 IMFD Input capture/
compare
match flag D
[Setting conditions]
• When TRDCNT = GRD and GRD is functioning
as output compare register
• When TRDCNT = GRD while the FTIOD pin
operates in PWM mode
• When TRDCNT = GRD in PWM3 mode, reset
synchronous PWM mode, or complementary
PWM mode
• When TRDCNT value is transferred to GRD by
input capture signal and GRD is functioning as
input capture register
[Clearing conditions]
• When the DTC is activated by an IMFD interrupt
and the DISEL bit in MRB of the DTC is 0
• When 0 is written to IMFD after reading IMFD = 1
R/W