Datasheet

Section 16 Timer RD
Page 526 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
3 ⎯ Reserved
This bit is read as 1. The write value should be 1.
⎯
2 IOA2 I/O control A2
Selects the GRA function.
0: GRA functions as an output compare register
1: GRA functions as an input capture register
R/W
1, 0 IOA[1:0] I/O control A1
and A0
When IOA2 = 0,
00: No output at compare match
01: 0 output to the FTIOA pin at GRA compare
match
10: 1 output to the FTIOA pin at GRA compare
match
11: Output toggles to the FTIOA pin at GRA compare
match
When IOA2 = 1,
00: Input capture to GRA at rising edge at the FTIOA
pin
01: Input capture to GRA at falling edge at the FTIOA
pin
1X: Input capture to GRA at rising and falling edges
at the FTIOA pin
R/W
[Legend]
X: Don't care.
Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings
in the IOA2 and IOB2 bits in TRDIORA and the IOC2 and IOD2 bits in TRDIORC of
both registers should be the same.
2. In PWM mode, PWM3 mode, complementary PWM mode, and reset synchronous
PWM mode, the settings of TRDIORA are invalid.
TRDIORA selects whether GRA or GRB is used as an output compare register or an input capture
register. When an output compare register is selected, the output setting is selected. When an input
capture register is selected, an input edge of an input capture signal is selected. TRDIORA also
selects the function of FTIOA or FTIOB pin.