Datasheet

Section 16 Timer RD
Page 524 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
2 to 0 TPSC[2:0] Time
prescaler 2 to
0
000: Internal clock: count by φ
001: Internal clock: count by φ/2
010: Internal clock: count by φ/4
011: Internal clock: count by φ/8
100: Internal clock: count by φ/32
101: External clock: count by FTIOA0 (TCLK) pin
input
110: Setting prohibited
111: Reserved (setting prohibited)
R/W
[Legend]
X: Don't care
Notes: 1. When GR functions as an output compare register, TRDCNT is cleared by compare
match. When GR functions as input capture, TRDCNT is cleared by input capture.
2. Synchronous operation is set by TRDMDR.
TRDCR selects a TRDCNT counter clock, an edge when an external clock is selected, and counter
clearing sources. Timer RD has a total of two TRDCR registers, one for each channel.