Datasheet

Section 16 Timer RD
Page 518 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
2 TOC0 Output level
select C0
0: 0 output at the FTIOC0 pin*
1: 1 output at the FTIOC0 pin*
R/W
1 TOB0 Output level
select B0
• In modes other than PWM3 mode
0: 0 output at the FTIOB0 pin*
1: 1 output at the FTIOB0 pin*
• In PWM3 mode
0: 1 output at the FTIOB0 pin on GRB_1
compare match and 0 output at the FTIOB0
pin on GRB_0 compare match
1: 0 output at the FTIOB0 pin on GRB_1
compare match and 1 output at the FTIOB0 pin
on GRB_0 compare match
R/W
0 TOA0 Output level
select A0
• In modes other than PWM3 mode
0: 0 output at the FTIOA0 pin*
1: 1 output at the FTIOA0 pin*
• In PWM3 mode
0: 1 output at the FTIOB0 pin on GRA_1
compare match and 0 output at the FTIOB0
pin on GRA_0 compare match
1: 0 output at the FTIOB0 pin on GRA_1
compare match and 1 output at the FTIOB0
pin on GRA_0 compare match
R/W
Note: * The change of the setting is immediately reflected in the output value.
TRDOCR selects the initial outputs before the first occurrence of a compare match. Note that bits
OLS1 and OLS0 in TRDFCR set these initial outputs in reset synchronous PWM mode and
complementary PWM mode.
In PWM3 mode, TRDOCR selects the output level of the FTIOA0 and FTIOB0 pins.