Datasheet

Section 16 Timer RD
Page 514 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
1, 0 CMD[1:0] Combination
mode 1 and 0
00: Channel 0 and channel 1 operate normally
01: Channel 0 and channel 1 are used together to
operate in reset synchronous PWM mode
10: Channel 0 and channel 1 are used together to
operate in complementary PWM mode
(transferred when TRDCNT_0 matches GRA_0)
11: Channel 0 and channel 1 are used together to
operate in complementary PWM mode
(transferred when TRDCNT_1 underflows)
Note: When the reset synchronous PWM mode or
complementary PWM mode is selected by
these bits, this setting has the priority to the
settings for PWM mode by each bit in
TRDPMR. Stop TRDCNT_0 and TRDCNT_1
before making settings for reset synchronous
PWM mode or complementary PWM mode.
R/W
Notes: 1. This bit is valid when both bits CMD1 and CMD0 are cleared to 0. When PWM3 mode
is selected, TRDPMR, TRDIORA, and TRDIORC are invalid.
2. The A/D converter registers should be set so that A/D conversion is started by an
external trigger.
• OLS1 bit (output level select 1)
This bit selects the output level for counter phase in reset synchronous PWM mode and
complementary PWM mode.
• OLS0 bit (output level select 0)
This bit selects the output level for normal phase in reset synchronous PWM mode and
complementary PWM mode.