Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 513 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.2.4 Timer RD Function Control Register (TRDFCR)
Address:
Bit:
Value after reset:
b7
PWM3
1
b6
STCLK
0
b5
ADEG
0
b4
ADTRG
0
b3
OLS1
0
b2
OLS0
0
b1
0
b0
0
H'FFFFD5
CMD[1:0]
Bit Symbol Bit Name Description R/W
7 PWM3 PWM3 mode
select
0: PWM3 mode is selected
1: PWM3 mode is not selected*
1
R/W
6 STCLK External clock
input select
0: External clock input is disabled
1: External clock input is enabled
R/W
5 ADEG A/D trigger
edge select
0: The A/D trigger signal is asserted when
TRDCNT_0 matches GRA_0 in complementary
PWM mode
1: The A/D trigger signal is asserted when
TRDCNT_1 underflows in complementary PWM
mode
R/W
4 ADTRG External
trigger disable
0: A/D trigger for PWM cycles is disabled in
complementary PWM mode
1: A/D trigger for PWM cycles is enabled in
complementary PWM mode*
2
R/W
3 OLS1 Output level
select 1
0: Initial output is high and the active level is low.
1: Initial output is low and the active level is high.
R/W
2 OLS0 Output level
select 0
0: Initial output is high and the active level is low.
1: Initial output is low and the active level is high.
R/W