Datasheet

Section 16 Timer RD
Page 510 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
0 STR0 Channel 0 counter
start
0: TRDCNT_0 stops counting.
1: TRDCNT_0 starts counting.
[Setting conditions]
• When 1 is written in STR0
• When the specified event is occurred after
ELOPA of the event link controller is selected
counting by timer RD_0 for channel 0.
[Clearing conditions]
• When 0 is written in STR0 while CSTPN0 = 1
• When the compare match A1 signal is
generated while CSTPN0 = 0
R/W
Note: Use a MOV instruction to modify this register.