Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 509 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.2.1 Timer RD Start Register (TRDSTR)
Address:
Bit:
Value after reset:
b7
⎯
1
b6
⎯
1
b5
⎯
1
b4
⎯
1
b3
CSTPN1
1
b2
CSTPN0
1
b1
STR1
0
b0
STR0
0
H'FFFFD2
Bit Symbol Bit Name Description R/W
7 to 4 ⎯ Reserved These bits are read as 1. The write value should
be 1.
⎯
3 CSTPN1 Channel 1 counter
stop
0: Counting is stopped on a compare match of
TRDCNT_1 and GRA_1
1: Counting is continued on a compare match of
TRDCNT_1 and GRA_1
Set this bit to 1 to restart counting after the
counting has been stopped on a compare match.
R/W
2 CSTPN0 Channel 0 counter
stop
0: Counting is stopped on a compare match of
TRDCNT_0 and GRA_0
1: Counting is continued on a compare match of
TRDCNT_0 and GRA_0
Set this bit to 1 to restart counting after the
counting has been stopped on a compare match.
R/W
1 STR1 Channel 1 counter
start
0: TRDCNT_1 stops counting.
1: TRDCNT_1 starts counting.
[Setting conditions]
• When 1 is written in STR1
• When the specified event is occurred after
ELOPB of the event link controller is selected
counting by timer RD_0 for channel 1.
[Clearing conditions]
• When 0 is written in STR1 while CSTPN1 = 1
• When the compare match A1 signal is
generated while CSTPN1 = 0
R/W