Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 493 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.4.8 Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 15.35 shows the status flag clearing timing.
IMFA to IMFD
Write signal
Address
φ
TRCSR address
TRCSR write cycle
T1 T2
Figure 15.35 Timing of Status Flag Clearing by CPU