Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 489 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.4.3 Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TRCIOR0 and TRCIOR1. Figure 15.29 shows the timing when the falling edge is selected.
TRCCNT
Input capture
input
φ
N-1
N N + 1 N + 2
N
GRA to GRD
Input capture
signal
Figure 15.29 Input Capture Input Signal Timing
15.4.4 Timing of Counter Clearing by Compare Match
Figure 15.30 shows the timing when the counter is cleared by compare match A. When the GRA
value is N, the counter counts from 0 to N, and its cycle is N + 1.
GRA
TRCCNT
φ
N
N H'0000
Compare
match signal
Figure 15.30 Timing of Counter Clearing by Compare Match