Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 481 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.3.4 Digital Filtering Function for Input Capture Inputs
Input signals on the FTIOA to FTIOD and TRGC pin can be input via the digital filters. The
digital filter includes three latches connected in series and a match detector circuit. The input
signals on the FTIOA to FTIOD or TRGC pins are using on the sampling clock specified by the
DFCK1 and DFCK0 bits in TRCDF. When outputs of the three latches match, the match detector
circuit outputs the signal level of the input. Otherwise, the output remains unchanged. That is,
when a pulse width is equal to or greater than three sampling clock cycles, the pulse is input as a
signal. When a pulse width is less than three sampling clock cycles, the pulse is considered as
noise to be removed.
φ/32
FTCI
φ/8
φ/4
φ/2
φ
φ
CKS2 to
CKS0
DFCK1 and
DFCK0
DFTRG and
DFA to DFD
IOA[1:0] to
IOD[1:0]
Sampling clock
φ/32
φ/8
φ
Match
detector
circuit
Selecter
Edge
detecting
circuit
Sampling clock
FTIOA to FTIOD
or TRGC
input signal
C
Latch
DQ
C
Latch
DQ
C
Latch
DQ
C
Latch
D
Q
FTIOA to FTIOD
and TRGC
input signals
Digital-filtered signal
Cycle of a clock specified
by CKS2 to CKS0
or DFCK1 and DFCK0
Signal change is not output unless
signal levels match three times.
Signal propagation delay:
5 sampling clocks
C
Latch
DQ
Figure 15.22 Block Diagram of Digital Filter