Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 479 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
The value of TRCCNT
H'FFFF
H'0000
GRA
GRB
GRC
CTS
High
FTIOB
FTIOA/TRGC
FTIOB
(Output transformation
when TOB = 0)
(Output transformation
when TOB = 1)
Time
Figure 15.19 Example of Stopping Operation of the Counter in PWM2 Mode
The following is an example of output operation of the one-shot pulse waveform in PWM2 mode.
When the TRGC input is disabled by TRCCR2 (clearing the TCEG1 and TCEG0 bits to 0),
TRCCNT is set to stop counting-up on compare match A with GRA (setting the CSTP bit in
TRCCR2 to 1), TRCCNT is cleared on compare match A (setting the CCRL bit in TRCCR1 to 1),
and the initial value of the output signal is set to 0 by TRCCR1 (clearing the TOB bit to 0),
TRCCNT starts counting when the CTS bit in TRCMR is set to 1. Then, TRCCNT is cleared to
H'0000 on a compare match with GRA and stops counting, and the one-shot pulse waveform is
output. Figure 15.20 shows such an example.
The value of TRCCNT
H'FFFF
H'0000
GRA
GRB
GRC
CTS
High
FTIOB
FTIOA/TRGC
Time
Figure 15.20 Example (1) of Output Operation of One-Shot Pulse Waveform
in PWM2 Mode