Datasheet

Section 15 Timer RC
Page 478 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
The value of TRCCNT
H'FFFF
H'0000
GRA
GRB
GRC
FTIOB
FTIOA/TRGC
FTIOB
When TOB = 0, the trigger input is ignored
while the FTIOB pin is driven high, whereas
when TOB = 1, the trigger input is ignored
while the FTIOB pin is driven low
GRD
GRB
A
ABCD
BC
D
(Output transformation
when TOB = 0)
(Output transformation
when TOB = 1)
Time
Figure 15.17 Example (1) of TRGC Synchronous Operation in PWM2 Mode
The value of TRCCNT
H'FFFF
H'0000
GRA
GRB
GRC
CTS
GRD
GRB
Data written from
the CPU to GRD
Data copied from
GRD to GRB
A
ABAA
BC
A
High
FTIOB
FTIOA/TRGC
FTIOB
Time
(Output transformation
when TOB = 0)
(Output transformation
when TOB = 1)
Figure 15.18 Example (2) of TRGC Synchronous Operation in PWM2 Mode
The following is an example of stopping operation of the counter in PWM2 mode. When the
CSTP bit in TRCCR2 is set to 1 and the CCLR bit in TRCCR1 is set to 1, TRCCNT is cleared to
H'0000 on a compare match with GRA and stops counting. Moreover, TRCCNT is forcibly
stopped and cleared to the initial value when the CTS bit in TRCMR is cleared to 0. Figure 15.19
shows such an example when the TOB bit in TRCCR1 is cleared to 0 and set to 1.