Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 473 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Figures 15.12 and 15.13 show examples of the output of PWM waveforms with duty cycles of 0%
and 100%.
TRCCNT
GRA
H'0000
FTIOB
Time
GRB
Duty cycle 0%
GRB changed
GRB changed
TRCCNT
GRA
H'0000
FTIOB
Time
GRB
Duty cycle 100%
GRB changed
GRB changed
TRCCNT
GRA
H'0000
FTIOB
Time
GRB
Duty cycle 100%
GRB changed
GRB changed
GRB changed
Duty cycle 0%
GRB changed
Output levels of FTIOB are not changed when compare
matches of cycle register and duty cycle register occur
simultaneously.
Output levels of FTIOB are not changed when compare
matches of cycle register and duty cycle register occur
simultaneously.
Figure 15.12 PWM Mode Example (Initial Output Set to 0)