Datasheet

Section 15 Timer RC
Page 472 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Figure 15.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TRCCNT is cleared on compare match A, and the
FTIOB pin outputs 1 on compare match B and 0 on compare match A.
Due to the buffer operation, the FTIOB output levels are changed and the value of buffer register
GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every
time compare match B occurs.
TRCCNT value
GRA
H'0000
GRD
Time
GRB
H'0200 H'0520
FTIOB
H'0200
H'0450
H'0520
H'0450
GRB
H'0450 H'0520
H'0200
Figure 15.11 Buffer Operation Example (Output Compare)