Datasheet

Section 15 Timer RC
Page 466 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Periodic counting operation can be performed when GRA is set as an output compare register and
the CCLR bit in TRCCR1 is set to 1. When the counter value matches GRA, TRCCNT is cleared
to H'0000, and the IMFA flag in TRCSR is set to 1. If the corresponding IMIEA bit in TRCIER is
set to 1, an interrupt request is generated. TRCCNT continues counting from H'0000. Figure 15.3
shows an example of periodic counting.
TRCCNT
GRA
H'0000
CTS bit
IMFA
Time
Flag cleared
by software
Figure 15.3 Periodic Counter Operation
By setting a general register as an output compare register, the specified level of a signal can be
output on the FTIOA, FTIOB, FTIOC, or FTIOD pin on compare match A, B, C, or D. The output
level can be selected from 0, 1, or toggle. Figure 15.4 shows an example of TRCCNT functioning
as a free-running counter. In this example, 1 is output on compare match A and 0 is output on
compare match B. When the signal level is already at the selected output level, it is not changed
on a compare match.
TRCCNT
H'FFFF
H'0000
FTIOA
FTIOB
Time
GRA
GRB
No change No change
No change No change
Figure 15.4 0 and 1 Output Example (TOA = 0, TOB = 1)