Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 449 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.2.4 Timer RC Interrupt Enable Register (TRCIER)
b7
OVIE
0
b6
⎯
1
b5
⎯
1
b4
⎯
1
b3
IMIED
0
b2
IMIEC
0
b1
IMIEB
0
b0
IMIEA
0
H'FFFF8C
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 OVIE Timer overflow
interrupt
enable
0: An interrupt (FOVI) requested by the OVF flag in
TRCSR is disabled.
1: An interrupt (FOVI) requested by the OVF flag in
TRCSR is enabled.
R/W
6 to 4 ⎯ Reserved These bits are read as 1. The write value should be
1.
⎯
3 IMIED Input capture/
compare
match interrupt
enable D
0: An interrupt (IMID) requested by the IMFD flag in
TRCSR is disabled.
1: An interrupt (IMID) requested by the IMFD flag in
TRCSR is enabled.
R/W
2 IMIEC Input capture/
compare
match interrupt
enable C
0: An interrupt (IMIC) requested by the IMFC flag in
TRCSR is disabled.
1: An interrupt (IMIC) requested by the IMFC flag in
TRCSR is enabled.
R/W
1 IMIEB Input capture/
compare
match interrupt
enable B
0: An interrupt (IMIB) requested by the IMFB flag in
TRCSR is disabled.
1: An interrupt (IMIB) requested by the IMFB flag in
TRCSR is enabled.
R/W
0 IMIEA Input capture/
compare
match interrupt
enable A
0: An interrupt (IMIA) requested by the IMFA flag in
TRCSR is disabled.
1: An interrupt (IMIA) requested by the IMFA flag in
TRCSR is enabled.
R/W