Datasheet

Section 14 Timer RB
Page 440 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
14.5 Usage Notes
1. In programmable one-shot generation mode and programmable wait one-shot generation
mode, if the counting is stopped by clearing the TSTART bit in TRBCR to 0, the timer counter
holds a count value, and then stops.
2. After 1 is written to the TSTART bit when the counting is stopped, the TCSTF bit remains 0
for the number of cycles of the count source. The timer RB related registers*, with the
exception of the TRBCR for reading should not be accessed until the TCSTF bit is set to 1.
After 0 is written to the TSTART bit during counting, the TCSTF bit remains 1 for the number
of cycles of the count source. The timer RB related registers*, with the exception of the
TRBCR for reading should not be accessed until the TCSTF bit is cleared to 0.
Note: Timer RB-related registers refer to registers TRBCR, TRBOCR, TRBIOC, TRBMR,
TRBPRE, TRBSC, and TRBPR.
3. TRBPRE and TRBPR should not be set to H'00 at the same time.
4. When rewriting the bits TRBPRE, TRBPR, and TRBSC at TSTART = 0, set TSTART to 1
after the passage of at least 2 cycles of the system clock φ.
5. When TSTART = 1 or TCSTF = 1, TRBIOC, or TRBMR should not be rewritten.
6. When writing 1 to the TOSST bit, read the TCSTF bit and write by verifying the value 1.
7. In programmable waveform generation mode or programmable wait one-shot mode, make sure
another write to TRBSC does not occur between writing to TRBPR and reloading to the
counter.
8. When writing successively to TRBPRE during counting (TCSTF=1), allow at least four cycles
of the clock source for counting as the minimum interval for writing
9. When writing successively to TRBPR and TRBSC during counting (TCSTF=1), allow at least
four cycles of the clock source for counting as the minimum interval for writing
10. When 1 is written to the TOSST or TOSSP bit in TRBOCR, the value of the TOSSTF bit
changes accordingly after 1 to 2 cycles of the source for counting. If 1 is written to the TOSSP
bit during the period between the TOSST bit having been set to 1 and the value of the TOSSTF
bit becoming 1, the value of the TOSSTF bit will become 0 in some cases and 1 in others,
depending on the internal state. In the same way, if 1 is written to the TOSST bit during the
period between the TOSSP bit having been set to 1 and the value of the TOSSTF bit becoming
0, whether the value of the TOSSTF bit will become 0 or 1 is not defined.
11. When values for TRBPRE and TRBPR are successively read out from the same register, allow
at least two cycles of the clock source for counting as the minimum interval for reading
12. When timer RB selects the timer RA underflow as a count source, be sure to set timer RA to
timer mode, pulse output mode, or event counter mode.