Datasheet

Section 14 Timer RB
REJ09B0465-0300 Rev. 3.00 Page 439 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
14.3.7 Operation through an Event Link
Using the event link controller (ELC), timer RB can be made to operate in the following ways in
relation to events occurring in other modules.
(1) Starting Counter Operation
The start of counting operations by timer RB can be selected by the ELOPA register of the ELC.
When the event specified in ELSR1 occurs, the TSTART bit in the TRBCR is set to 1, which
starts counting by timer RB. However, if the specified event occurs when the TCSTF flag has
already been set to 1, that event is not effective.
(2) Counting Events
The counting of events by timer RB can be selected by the ELOPA register of the ELC. When the
event specified in ELSR1 occurs, event counter operation proceeds with that event as the source to
drive counting, regardless of the setting in the TCK[2:0] bits in TRBMR. When event-counter
operation is to be employed, set the TSTART bit in TRBCR to 1 beforehand. When the value of
the counter is read, the value read out is the actual number of input events minus three.
14.4 Interrupt Request
This module provides a timer RB interrupt enable bit (the TRBIE bit in TRBIR) and a timer RB
interrupt request flag (the TRBIF bit in TRBIR). An interrupt request is issued to the CPU when
the TRBIE bit is set to 1 while the TRBIF bit is 1, or when the TRBIE bit changes from 0 to 1
while the TRBIF bit is 1. Since the condition under which the TRBIF bit is set varies with
operation modes, see the explanation on the TRBIF bit and the description of the various operation
modes.