Datasheet

Section 14 Timer RB
REJ09B0465-0300 Rev. 3.00 Page 421 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
14.2.1 Timer RB Control Register (TRBCR)
b7
⎯
0
b6
⎯
0
b5
⎯
0
b4
⎯
0
b3
⎯
0
b2
TSTOP
0
b1
TCSTF
0
b0
TSTART
0
H'FFFFA0
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 to 3 ⎯ Reserved
These bits are read as 0. The write value should
be 0.
⎯
2 TSTOP Count forced stop
0: Timer RB counting is continued.
1: Timer RB counting is forcedly stopped.
R/W
1 TCSTF Count status flag 0: Timer RB counting is stopped.
1: Timer RB counting is in progress.
[Setting conditions]
• When 1 is written to TSTART and counting is
started.
• The start of counting after ELOPA of the event
link controller is selected counting by timer
RB, the specified event is occurred, and the
TSTART bit is set to 1.
[Clearing conditions]
• When 0 is written to TSTART and counting is
stopped.
• When 1 is written to TSTOP and counting is
stopped.
R
0 TSTART Count start
0: Timer RB counting is stopped.
1: Timer RB counting is started.
R/W
Notes: 1. The timer RB registers should not be accessed until the TCSTF bit changes after the
TSTART bit is set, apart from TRBCR which can be read at any time during timer
operation.
2. A MOV instruction should be used to write to this register.
• TSTOP bit (count forced stop)
Setting this bit to 1 stops counting forcibly. At this time, the counter of the timer RB prescaler
and the timer RB counter are initialized. Also, bits TSTART and TCSTF in TRBCR, bits
TOSSTF, TOSSP, TOSST in TRBOCR, and TRBO outputs are initialized. The reload register
of the prescaler and the timer RB counter are hold. This bit is always read as 0.