Datasheet

Section 13 Timer RA
Page 410 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
13.2.6 Timer RA Timer Register (TRATR)
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
H'FF06F4
Bit:
Address:
Value after reset:
TRATR consists of a reload register and an 8-bit counter, each with an initial value of H'FF.
TRATR performs a down-count of the prescaler underflows. When an underflow occurs in
TRATR, the value of the reload register is loaded to the counter and a timer RA interrupt request
is generated at the same time.
The reload register and the counter are assigned to the same address. On write, a value is written
to the reload register, and on read, a counter value is read. However, on read in pulse cycle
measurement mode, a value in the read buffer is read. During a write to TRATR the load timing
from the reload register to the counter differs between counting in progress and counting stopped.
Writing to TRATR when counting is stopped causes the data to be written to both the reload
register and the counter. Writing to TRATR during counting causes the new value to be written to
the reload register in synchronization with an underflow of the prescaler first after four counts of
the count source, and to be loaded to the counter in synchronization with the next underflow of the
prescaler.
TRAPRE and TRATR should not be set to H'00 at the same time.