Datasheet

Section 13 Timer RA
Page 408 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
13.2.4 Timer RA Interrupt Enable Status Register (TRAIR)
b7
TRAIE
0
b6
TRAIF
0
b5
⎯
0
b4
⎯
0
b3
⎯
0
b2
⎯
0
b1
⎯
0
b0
⎯
0
H'FF06F5
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 TRAIE Timer RA
interrupt
request enable
0: Timer RA interrupt requests are disabled.
1: Timer RA interrupt requests are enabled.
R/W
6 TRAIF Timer RA
interrupt
request flag
[Setting conditions]
• When the timer RA underflows.
• When the input pulse measurement is completed in
pulse width measurement mode.
• When the timer RA prescaler underflows at the
second time after a valid edge of measurement
pulse is input, in pulse cycle measurement mode.
[Clearing condition]
• When 1 is read from the bit and then 0 is written to.
R/W
5 to 0 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯