Datasheet

Section 13 Timer RA

Page 404 of 982 REJ09B0465-0300 Rev. 3.00

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

Bit Symbol Bit Name Description R/W

1 TCSTF Timer RA

count status

flag

0: Timer RA counting has been stopped.

1: Timer RA counting is in progress.

[Setting condition]

• When 1 is written to TSTART and counting is

started.

• The start of counting after ELOPA of the event link

controller is selected counting by timer RA, the

specified event is occurred, and the TSTART bit is

set to 1.

[Clearing condition]

• When 0 is written to TSTART and counting is

stopped.

• When 1 is written to TSTOP and counting is

stopped.

0 TSTART Timer RA

count start

0: Timer RA counting is stopped.

1: Timer RA counting is started.

R/W

Notes: 1. A MOV instruction should be used to write 0 to this register.

2. The timer RA registers should not be accessed until the TCSTF bit changes after the

TSTART bit is set, apart from TRACR which can be read at any time during timer

operation.

TRACR controls the timer RA counter and indicates the timer RA state.

• TSTOP bit (timer RA count forced stop)

Setting this bit to 1 initializes the counter of the timer and the prescaler, bits TSTART and

TCSTF, and timer outputs. This bit is always read as 0.