Datasheet

Section 12 Event Link Controller
Page 398 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
12.3.6 Event-Generation Timer
The event-generation timer can generate an event at specified interval. The generated event can be
connected to another module. The features of the timer are given below.
• The interval can be generated using the 16-bit free-running counter.
• The delay time (of 0 to 3 counter clock cycles) can be set, which is the time from the set event-
generation timing (= interval) to actual generation of the event.
• Four-channel event output is available (figure 12.8).
Internal clock
(φ/8192 to φ)
One cycle
32768 cycles
ELTMCNT
ELTMCR
ELTMSA
ELTMSB
ELTMDR
Channel 0
Channel 1
Channel 2
Channel 3
Internal data bus
Output delay
circuit 0
Output delay
circuit 1
Output delay
circuit 2
Output delay
circuit 3
ELC timer event 0
ELC timer event 1
ELC timer event 2
ELC timer event 3
φELC
Figure 12.7 Block Diagram of Event-Generation Timer