Datasheet

Section 12 Event Link Controller
REJ09B0465-0300 Rev. 3.00 Page 381 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
12.2.9 Event Link Port Setting Registers 0 to 3 (PEL0 to PEL3)
b7
⎯
1
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
H'FF06AD to H'FF06B0
PSMn[1:0]
PSPn[4:3] PSPn[2:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯
6
5
PSMn[1:0] Event link
specification
• For the output port, data to be output from the
port is specified.
00: 0 is output when the event is input.
01: 1 is output when the event is input.
1X: The toggled (inverted) value is output when
the event is input.
• For the input port, the edge on which the event is
to be output is specified.
00: Event is output upon detection of the rising
edge.
01: Event is output upon detection of the falling
edge.
1X: Event is output upon detection of both the
rising and falling edge.
R/W
4
3
PSPn[4:3] Port number
specification
00: Do not set this value.
01: Port 3 (corresponding to PGR1)
10: Port 6 (corresponding to PGR2)
11: Do not set this value.
R/W
2 PSPn2 R/W
1 PSPn1 R/W
0 PSPn0
Bit number
specification
A bit number in an 8-bit port is specified.
R/W
[Legend]
n: 0 to 3
X: Don't care.
PEL specifies the 1-bit port (hereinafter referred to as a single-port) to which an event is to be
linked, the port operation upon the event signal input, and the conditions of event generation. With
this LSI, a total of four bits in either port 3 or port 6 (8-bit ports) can be specified as single-ports.