Datasheet

Section 12 Event Link Controller
REJ09B0465-0300 Rev. 3.00 Page 379 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
12.2.7 Port-Group Control Registers 1 and 2 (PGC1 and PGC2)
b7
⎯
1
b6
0
b5
0
b4
0
b3
⎯
1
b2
PGCOVEn
0
b1
0
b0
0
H'FF06A6, H'FF06A7
PGCOn[2:0] PGCIn[1:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯
6 to 4 PGCOn[2:0] Port group
operation
select
000: 0 is output when the event is input.
001: 1 is output when the event is input.
010: The toggled (inverted) value is output when the
event is input.
011: The buffer value is output when the event is
input.
1XX: The bit value is sifted out in the group (from
MSB to LSB) when the event is input.
R/W
3 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯
2 PGCOVEn PDBF
overwrite
0: Overwriting PDBF is disabled.
1: Overwriting PDBF is enabled.
R/W
1, 0 PGCIn[1:0] Event output
edge select
00: Event is generated upon detection of the rising
edge of the external input signal.
01: Event is generated upon detection of the falling
edge of the external input signal.
1X: Event is generated upon detection of both the
rising and falling edge of the external input
signal.
R/W
[Legend]
n: 1 or 2
X: Don't care.
For the output port-group, PGC specifies the form of outputting the signal externally via the port
when the event signal is input. For the input port-group, PGC enables/disables overwriting of
PDBF and specifies the conditions of event generation (edge of the externally input signal).
The correspondence between PGC and ports is shown in table 12.3.