Datasheet

Section 11 Data Transfer Controller (DTC)
Page 366 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
First data
transfer register
information
Second data
transfer register
information
Chain transfer
(counter = 0)
Upper 8 bits
of DAR
Input buffer
Input circuit
Figure 11.13 Chain Transfer when Counter = 0