Datasheet

Section 11 Data Transfer Controller (DTC)
Page 362 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 11.9 Number of States Required for Each Execution Status
Object to be Accessed
On-
Chip
RAM
On-
Chip
ROM
Internal I/O Register
Bus width 32 16 8 16
Access states 1 1 2 3 4 2 3 4
Vector read S
I
1 1 2 3 4 2 3 4 Execution
state
Register information
read/write S
J
1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Byte data read S
K
1 1 2 3 4 2 3 4
Word data read S
K
1 1 4 6 8 2 3 4
Byte data write S
L
1 1 2 3 4 2 3 4
Word data write S
L
1 1 4 6 8 2 3 4
Internal operation S
M
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1 +
1).
Number of execution states = I · S
I
+ Σ (J · S
J
+ K · S
K
+ L · S
L
) + M · S
M
For example, when the DTC vector address table is located in on-chip ROM and data is
transferred from the on-chip ROM to an internal I/O register (two-state access) in normal mode,
the time required for the DTC operation is 13 states. The time from activation to the end of the
data write is 10 states.