Datasheet

Section 11 Data Transfer Controller (DTC)
Page 358 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
First block
Transfer
Block area
Nth block
DAR
or
SAR
SAR
or
DAR
Figure 11.8 Memory Mapping in Block Transfer Mode
11.5.4 Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB
can be set independently.
Figure 11.9 shows the operation of chain transfer. When activated, the DTC reads the register
information start address stored at the vector address, and then reads the first register information
at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is
1, the next register information, which is located consecutively, is read and transfer is performed.
This operation is repeated until the end of data transfer of register information with CHNE = 0.
Setting both the CHNE bit and CHNS bit to 1 enables execution of chain transfer only when the
transfer counter value is 0.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.