Datasheet

Section 11 Data Transfer Controller (DTC)
REJ09B0465-0300 Rev. 3.00 Page 357 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
SAR
or
DAR
DAR
or
SAR
Repeat area
Transfer
Figure 11.7 Memory Mapping in Repeat Mode
11.5.3 Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 11.7 lists the register function in block
transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed according to the register
information. From 1 to 65,536 transfers can be specified. Once the specified number of transfers
has ended, a CPU interrupt is requested.
Table 11.7 Register Function in Block Transfer Mode
Name Abbreviation Function
DTC source address register SAR Designates source address
DTC destination address register DAR Designates destination address
DTC transfer count register AH CRAH Holds block size
DTC transfer count register AL CRAL Designates block size count
DTC transfer count register B CRB Designates transfer count