Datasheet

Section 11 Data Transfer Controller (DTC)
Page 340 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
11.2.2 DTC Mode Register B (MRB)
b7
CHNE
⎯
b6
DISEL
⎯
b5
CHNS
⎯
b4
⎯
⎯
b3
⎯
⎯
b2
⎯
⎯
b1
⎯
⎯
b0
⎯
⎯
⎯
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 CHNE DTC chain
transfer
enable
0: Disables chain transfer.
1: Enables chain transfer.
⎯
6 DISEL DTC interrupt
select
0: Generates an interrupt request to the CPU only
when the specified data transfer has been
completed.
1: Generates an interrupt request to the CPU every
time after the DTC transfer has been completed.
⎯
5 CHNS Chain transfer
select
0: Performs chain transfer consecutively.
1: Performs chain transfer only when transfer counter
= 0
⎯
4 to 0 ⎯ Reserved These bits have no effect on DTC operation. The
write value should be 0.
⎯
MRB selects the DTC operating mode.
• CHNE bit (DTC chain transfer enable)
When this bit is set to 1, a chain transfer will be performed. For details, see section 11.5.4,
Chain Transfer.
In the data transfer with CHNE set to 1, determination of the end of the specified number of
transfers, clearing of the activation source flag, and clearing of DTCER are not performed.
• DISEL bit (DTC interrupt select)
When this bit is set to 1, a CPU interrupt request is generated every time the DTC transfer is
performed (the interrupt source flags as the activation source are not cleared to 0 by the DTC).
When this bit is cleared to 0, a CPU interrupt request is generated at the time when the
specified number of data transfers ends (the interrupt source flags as the activation source is
cleared to 0 by the DTC).