Datasheet

Section 11 Data Transfer Controller (DTC)
Page 338 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
11.2.1 DTC Mode Register A (MRA)
b7
⎯
b6
⎯
b5
⎯
b4
⎯
b3
⎯
b2
⎯
b1
DTS
⎯
b0
Sz
⎯
⎯
SM[1:0] DM[1:0] MD[1:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7
6
SM[1:0] Source
address mode
1 and 0
0×: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
⎯
5
4
DM[1:0] Destination
address mode
1 and 0
0×: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
⎯
3
2
MD[1:0] DTC mode 1
and 0
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
⎯
1 DTC DTC transfer
mode select
0: Destination side is repeat area or block area.
1: Source side is repeat area or block area.
⎯
0 Sz DTC data
transfer size
0: Byte-size transfer
1: Word-size transfer
⎯
Legend:
×: Don't care