Datasheet

Section 11 Data Transfer Controller (DTC)
Page 336 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
The DTC's register information is stored in the on-chip RAM. A 32-bit bus connects the DTC to
the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC register information.
Interrupt
request
Interrupt controller DTC
Internal address bus
DTC activation
request
Control logic
Register information
MRA MRB
CRA CRB
DAR SAR
CPU interrupt
request
On-chip
RAM
Internal data bus
DTCERA
to
DTCERH
DTVECR
Figure 11.1 Block Diagram of DTC