Datasheet

Section 10 I/O Ports
REJ09B0465-0300 Rev. 3.00 Page 333 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
10.10.3 Port Data Register J (PDRJ)
b7
⎯
0
b6
⎯
0
b5
⎯
0
b4
⎯
0
b3
⎯
0
b2
⎯
0
b1
PDRJ1
0
b0
PDRJ0
0
H'FFFFEC
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 to 2 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯
1 PDRJ1 Port J1 data R/W
0 PDRJ0 Port J0 data
0: Low level
1: High level
PDRJ is a register that stores output data for port J
pins. When PCRJ bits are set to 1, the values stored in
PDRJ are output.
When PDRJ is read while PCRJ bits are set to 1, the
values stored in PDRJ are read. If PDRJ is read while
PCRJ bits are cleared to 0, the pin states are read
regardless of the value stored in PDRJ.
R/W