Datasheet

Section 10 I/O Ports
Page 316 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
10.8.3 Port Data Register A (PDRA)
b7
PDRA7
0
b6
PDRA6
0
b5
PDRA5
0
b4
PDRA4
0
b3
⎯
0
b2
⎯
0
b1
⎯
0
b0
⎯
0
H'FFFFE9
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 PDRA7 Port A7 data R/W
6 PDRA6 Port A6 data R/W
5 PDRA5 Port A5 data R/W
4 PDRA4 Port A4 data
0: Low level
1: High level
PDRA is a register that stores output data for port A
pins. When PCRA bits are set to 1, the values
stored in PDRA are output.
When PDRA is read while PCRA bits are set to 1,
the values stored in PDRA are read. If PDRA is
read while PCRA bits are cleared to 0, the pin
states are read regardless of the value stored in
PDRA.
R/W
3 to 0 ⎯ Reserved These bits are read as 0. The write value should be
0.
⎯