Datasheet

Section 10 I/O Ports
Page 298 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
10.5.3 Port Data Register 6 (PDR6)
b7
PDR67
0
b6
PDR66
0
b5
PDR65
0
b4
PDR64
0
b3
PDR63
0
b2
PDR62
0
b1
PDR61
0
b0
PDR60
0
H'FFFFE5
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 PDR67 Port 67 data R/W
6 PDR66 Port 66 data R/W
5 PDR65 Port 65 data R/W
4 PDR64 Port 64 data R/W
3 PDR63 Port 63 data R/W
2 PDR62 Port 62 data R/W
1 PDR61 Port 61 data R/W
0 PDR60 Port 60 data
0: Low level
1: High level
PDR6 is a register that stores output data for port 6
pins. When PCR6 bits are set to 1, the values
stored in PDR6 are output.
When PDR6 is read while PCR6 bits are set to 1,
the values stored in PDR6 are read. If PDR6 is read
while PCR6 bits are cleared to 0, the pin states are
read regardless of the value stored in PDR6.
R/W