Datasheet

Section 10 I/O Ports
Page 294 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
10.4.5 Port Drive Control Register 5 (PDVR5)
b7
⎯
0
b6
⎯
0
b5
PDVR55
0
b4
PDVR54
0
b3
PDVR53
0
b2
PDVR52
0
b1
PDVR51
0
b0
PDVR50
0
H'FF0034
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 ⎯ Reserved ⎯
6 ⎯ Reserved
This bit is read as 0. The write value should be 0.
⎯
5 PDVR55 Port 55 drive
control
R/W
4 PDVR54 Port 54 drive
control
R/W
3 PDVR53 Port 53 drive
control
R/W
2 PDVR52 Port 52 drive
control
R/W
1 PDVR51 Port 51 drive
control
R/W
0 PDVR50 Port 50 drive
control
0: Normal output
1: High-current drive output
PDVR5 is a register that controls drive capability of
the output pins in a bit unit.
When pins P56 and P57 are set as general output,
they function as NMOS push-pull output and thus
drive capability cannot be selected for them.
R/W
Note: When pins P56 and P57 are set as general output, they function as NMOS push-pull output,
and have characteristics different from those of other CMOS outputs. When set as SDA and
SCL of IIC2, they function as NMOS open-drain output. For details, see section 28,
Electrical Characteristics.