Datasheet

Section 10 I/O Ports
Page 274 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
10.1.3 Port Data Register 1 (PDR1)
b7
PDR17
0
b6
PDR16
0
b5
PDR15
0
b4
PDR14
0
b3
PDR13
0
b2
PDR12
0
b1
PDR11
0
b0
PDR10
0
H'FFFFE0
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 PDR17 Port 17 data R/W
6 PDR16 Port 16 data R/W
5 PDR15 Port 15 data R/W
4 PDR14 Port 14 data R/W
3 PDR13 Port 13 data R/W
2 PDR12 Port 12 data R/W
1 PDR11 Port 11 data R/W
0 PDR10 Port 10 data
0: Low level
1: High level
PDR1 is a register that stores output data for port 1
pins. When PCR1 bits are set to 1, the values
stored in PDR1 are output.
When PDR1 is read while PCR1 bits are set to 1,
the values stored in PDR1 are read. If PDR1 is read
while PCR1 bits are cleared to 0, the pin states are
read regardless of the value stored in PDR1.
In the H8S/20103 and H8S/20115 Groups, bits
PDR14 and PDR10 are reserved. Only 0 should be
written to these bits.
R/W