Datasheet

Section 1 Overview

Page 2 of 982 REJ09B0465-0300 Rev. 3.00

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

Classification

Module/

Function Description

CPU CPU

• 16-bit high-speed H8S/2000 CPU (CISC type)

Upwardly compatible with H8/300 and H8/300H CPUs at object

level

• General-register architecture (sixteen 16-bit general registers)

• Eight addressing modes

• 16-Mbyte address space

⎯ Program: 16 Mbytes available

⎯ Data: 16 Mbytes available

• 65 basic instructions including bit operation instructions,

multiply and divide instructions, bit manipulation instructions,

and others

• Minimum instruction execution time: 50 ns (for an ADD

instruction) while system clock φ = 20 MHz and

= 2.7 to 5.5 V

Operating

mode

Advanced single-chip mode

Interrupt

(source)

Interrupt

controller

(INTC)

• Nine external interrupt pins (NMI, and IRQ7 to IRQ0)

• Internal interrupt sources

⎯ 55 (H8S/20103 and H8S/20115 Groups)

⎯ 61 (H8S/20203 and H8S/20215 Groups)

⎯ 63 (H8S/20223 and H8S/20235 Groups)

• Two interrupt control modes (specified by the interrupt control

• Four interrupt priority orders specifiable (by setting the interrupt

priority register)

• Independent vector addresses

Clock Clock pulse

generator

(CPG)

• Two clock generation circuits: main and sub-clock oscillators

• One on-chip oscillator

⎯ Low speed: 125 kHz

• Three power-down modes: sleep mode, software standby

mode, and module standby mode