Datasheet

Section 7 ROM
Page 232 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Mode State
When Interrupt Request is
Received
When Watchdog Timer Reset,
LVD Reset, Software Reset, or
Pin Reset, Interrupt Request is
Generated
EW1 During erasure command
(erase-suspend function
not used)
Erasure is given priority,
keeping the interrupt
request waiting. When
erasure is completed,
execution of the interrupt
processing is started.
During erasure command
(erase-suspend function
used)
After the transition time to
erase-suspend mode,
erasure is suspended
starting execution of the
interrupt processing. When
the interrupt processing is
completed, setting the
FMSPREQ bit in FLMCR2
to 0 resumes erasure.
During programming
command
During lock-bit program
command
During blank checking
command
A software command is
given priority, keeping the
interrupt request waiting.
When the software
command is completed,
execution of the interrupt
processing is started.
Immediately after a reset is
generated, a software command
is forcibly terminated, and flash
memory and LSI are reset.
Because of the forced
termination, it might be
impossible to read correct values
from the block or address for
which the software command
has been executed; execute
erasure again after restarting and
confirm that erasure is completed
successfully.
Since the watchdog timer does
not stop even during command
execution, set the overflow time
of the watchdog timer longer
than the erasure/programming
execution time.
(3) Method of Access
When writing values to the protected bits indicated below, start by writing 0 to the bit and then
write 1 to it or by writing 1 to the bit and then write 0 to it. Do not allow the generation of any
interrupt or any access to other I/O registers between the two operations. For writing, always use
the MOV instruction.
(a) Bits that are set to 1 by writing 0 and then 1 consecutively
• FLMCR1: FMLBD and FMCMDEN bits
• FLMCR2: FMISPE and FMSPEN bits
(b) Bits that are cleared to 0 by writing 1 and then 0 consecutively
• DFPR: DFPR1 and DFPR0 bits