Datasheet

Section 7 ROM
REJ09B0465-0300 Rev. 3.00 Page 231 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
7.9 Usage Notes
(1) Prohibited Instruction
In EW0 mode, the following instruction cannot be used because it refers to the data in the flash
memory area.
• TRAPA
(2) Interrupts
Table 7.16 shows interrupt handling in CPU reprogramming mode.
Table 7.16 Interrupt Handling in CPU Reprogramming Mode
Mode State
When Interrupt Request is
Received
When Watchdog Timer Reset,
LVD Reset, Software Reset, or
Pin Reset, Interrupt Request is
Generated
EW0 During erasure command
During programming
command
During lock-bit program
command
During blank checking
command
Interrupts can be handled if
interrupt vectors are located
in the RAM. For details, see
section 4.2.7, Interrupt
vector offset register
(VOFR).
Immediately after a reset is
generated, a software command
is forcibly terminated, and flash
memory and LSI are reset.
Because of the forced
termination, it might be
impossible to read correct values
from the block or address for
which the software command
has been executed; execute
erasure again after restarting and
confirm that erasure is completed
successfully.
The watchdog timer does not
stop even during command
execution; initialize the timer
periodically.