Datasheet

Section 7 ROM
REJ09B0465-0300 Rev. 3.00 Page 215 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(2) Erasure
When H'20 is written in the first command cycle and H'D0 is written to any address in the block in
the second command cycle, erase/erase-verify of the specified block is automatically started.
Completion of erasure is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read as 0
during erasure, and read as 1 after erasure completion.
After erasure completion, the erasure result can be checked by reading the FMEBSF bit in
FLMSTR. (See the description in (9) below, Full Status Checking.)
Note that if the lock bit is 0 (locked) in the specified block and the FMLBD bit is 0 (lock bit
enabled), an erasure command is not accepted for the specified block.
Figures 7.14 and 7.15 show the flowcharts when the erase-suspend function is not used and when
used, respectively.
When the erase-suspend function is being employed and erasure is resumed immediately after a
period in erase-suspend mode, instruction fetching with normal incrimination of the program
counter will not be possible. To avoid this problem, add three NOP instructions immediately after
the instruction that writes FMSPREQ = 0. Furthermore, do not use the DTC when erasure has
been suspended in EW1 mode and the reprogramming control program has been allocated to
RAM.
In EW1 mode, do not execute this command for the block in which the reprogramming-control
program is located.
The FMRDY bit in FLMSTR changes to 0 when erasure is started, and changes to 1 when
completed.