Datasheet

Section 7 ROM
REJ09B0465-0300 Rev. 3.00 Page 213 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 7.11 Software Commands (in Byte Instructions: FMWUS = 0)
First Command
Cycle
Second
Command Cycle
Third Command
to Fifth
Command Cycle
Command Use in
Modes
Software
Command
Mode Addr. Data Mode Addr. Data Mode Addr. Data EW0 EW1
Erasure Write × H'20 Write BA H'D0 Possible Possible
Programming Write WA H'41 Write WA WD1 Write WA WD2
to
WD4
Possible Possible
Blank checking Write × H'25 Write BA H'D0 Possible Possible
Lock-bit program Write × H'77 Write BA H'D0 Possible Possible
Read-array Write × H'FF Possible ⎯
Clear-status Write × H'50 Possible Possible
Lock-bit reading Write × H'71 Read BA H'xx Possible Impossible
[Legend]
×: Arbitrary address in the user ROM area
xx: Eight-bit arbitrary data
BA: Arbitrary address in a block
WA: Programming address. (The lower two bits of an address are ignored. WA should be the
same in each command cycle.)
WDn: Programming data (8 bits)
(1) Initialization for CPU Reprogramming Mode
Before software commands are issued, settings for CPU reprogramming mode must be made and
issuing of software commands must be permitted.
Figure 7.13 shows initialization for CPU reprogramming mode.