Datasheet

Page xxiii of xxvi
22.2.5 SS Mode Register 2 (SSMR2) .............................................................................. 774
22.2.6 SS Enable Register (SSER) .................................................................................. 777
22.2.7 SS Status Register (SSSR).................................................................................... 778
22.2.8 SS Receive Data Register (SSRDR)..................................................................... 780
22.2.9 SS Transmit Data Register (SSTDR).................................................................... 780
22.2.10 SS Shift Register (SSTRSR)................................................................................. 780
22.3 Operation ........................................................................................................................... 781
22.3.1 Transfer Clock ...................................................................................................... 781
22.3.2 Relationship between Clock Polarity and Phase, and Data................................... 781
22.3.3 Relationship between Data Input/Output Pin and Shift Register.......................... 782
22.3.4 Communication Modes and Pin Functions ........................................................... 783
22.3.5 Operation in Clocked Synchronous Communication Mode ................................. 784
22.3.6 Operation in Four-Line Bus Communication Mode ............................................. 791
22.3.7 SCS Pin Control and Arbitration .......................................................................... 797
22.4 Interrupt Requests ..............................................................................................................798
22.5 Usage Notes ....................................................................................................................... 798
Section 23 Hardware LIN ..................................................................................799
23.1 Overview............................................................................................................................ 799
23.2 Register Configuration....................................................................................................... 800
23.2.1 LIN Control Register (LINCR)............................................................................. 800
23.2.2 LIN Status Register (LINST)................................................................................ 802
23.3 Operation ........................................................................................................................... 803
23.3.1 Master Mode......................................................................................................... 803
23.3.2 Slave Mode........................................................................................................... 806
23.3.3 Bus Conflict Detection Function .......................................................................... 811
23.3.4 Terminating Hardware LIN .................................................................................. 812
23.4 Interrupt Requests ..............................................................................................................813
23.5 Usage Note......................................................................................................................... 813
Section 24 A/D Converter..................................................................................815
24.1 Features.............................................................................................................................. 815
24.2 Register Description .......................................................................................................... 819
24.2.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7).................................................. 820
24.2.2 A/D Control/Status Register (ADCSR) ................................................................ 821
24.2.3 A/D Control Register (ADCR) ............................................................................. 823
24.2.4 A/D Mode Register (ADMR) ............................................................................... 825
24.2.5 Compare Data Register (CMPR) .......................................................................... 826
24.2.6 Compare Control/Status Register (CMPCSR)...................................................... 828
24.2.7 Compare Voltage Registers H and L (CMPVALH and CMPVALL)................... 830