Datasheet

Section 7 ROM
Page 166 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
7.4.3 Flash Memory Data Flash Protect Register (DFPR)
b7
⎯
0
b6
⎯
0
b5
⎯
0
b4
⎯
0
b3
⎯
0
b2
⎯
0
b1
DFPR1
0
b0
DFPR0
0
H'FF0662
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 to 2 ⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
1 DFPR1 Data flash B
E/W disable*
1
*
2
0: E/W of data flash B is enabled.
1: E/W of data flash B is disabled.
R/W
0 DFPR0 Data flash A
E/W disable*
1
*
2
0: E/W of data flash A is enabled.
1: E/W of data flash A is disabled.
R/W
Notes: 1. When setting the bit to 0, first set the bit to 1 and then immediately set the bit to 0; do
not allow any interrupt to be generated between these operations.
2. The DFPR bits are set to 1 when the FMCMDEN bit changes from 0 to 1.
DFPR enables/disables reprogramming of data flash areas in block units. Before reprogramming
the data flash areas, cancel the protection against reprogramming.
• DFPR1 bit (data flash B E/W disable)
Setting the DFPR1 bit to 1 disables software commands to be issued to data flash B. Setting
the DFPR1 bit to 0 enables software commands to be issued to data flash B.
• DFPR0 bit (data flash A E/W disable)
Setting the DFPR0 bit to 1 disables software commands to be issued to data flash A. Setting
the DFPR0 bit to 0 enables software commands to be issued to data flash A.